Typically, a semiconductor memory cell array includes a plurality of memory cells MC arranged in rows and columns and has a plurality of word lines WL.sub.1, WL.sub.2, . . . , and WL.sub.n which intersect bit line pairs BL.sub.1 and BL.sub.1 , BL.sub.2 and BL.sub.2 , BL.sub.3 and BL.sub.3 , . . . , and BL.sub.m, BL.sub.m . A conventional arrangement is depicted in FIG. 1. Memory cells are located at intersections of word lines WL and bit lines BL of a plurality of bit line pairs. Each memory cell includes a capacitor for storing data and a MOS transistor for switching. A sense amplifier section 2 including a plurality of sense amplifiers is responsive to a column selection signal CSL and transfers data between selected memory cells and a pair of data lines DL, DL.
An address buffer (not shown) receives external address signals which are decoded by a row decoder 4 and a column decoder 6. The row decoder 4 supplies a word line selecting signal RSL to a word line driver 8 which drives a word line selected in accordance with the address signals. A column decoder 6 supplies the column selecting signal CSL to the sense amplifier section 2 to effect data transfer between the data lines DL, DL and the column selected BL, BL in accordance with the addressed signals.
FIG. 2 is a detailed description of a portion of the arrangement shown in FIG. 1. Referring to FIG. 2, a word line WL.sub.i is connected to a gate of a MOS switching transistor Qs in a memory cell MC1. When the transistor Qs of memory cell MC1 is switched on by a signal on word line WLi, a data signal is transferred between the capacitor Cs of the memory cell MC1 and a bit line BL.sub.j connected to the memory cell MC1. In a reading operation, for example, the bit lines BL.sub.3 and BL.sub.3 of the illustrated bit line pair are pre-charged to a pre-charge voltage 1/2Vdd (1/2Vdd sensing). Similarly, a word line WL.sub.j is connected to a gate of a MOS switching transistor Qs in a memory cell MC2. When the transistor Qs of memory cell MC2 is switched on by a signal on word line WL.sub.j, a data signal is transferred between the capacitor Cs of the memory cell MC2 and a bit line BL.sub.j connected to the memory cell MC2. When data stored in one of the memory cells is read onto one of the bit lines, a potential difference is generated between bit lines BL.sub.J and BL.sub.j of the bit line pair. A bit line sense amplifier SA connected to the bit line pair BL.sub.j and BL.sub.j senses and amplifies this potential difference. As shown in FIG. 2, sense amplifier SA includes a CMOS flip-flop connected between the bit line BL.sub.j and BL.sub.j . The CMOS flip-flop which includes transistors Q1, Q2, Q3, and Q4 is connected via a PMOS transistor Q11 and an NMOS transistor Q12 to a power source Vdd and ground Vss, respectively. The gates of transistors Q11 and Q12 receive trigger signals S.sub.o and S.sub.o, respectively. Data signals are transferred between the bit lines BL.sub.j, BL.sub.j and the data lines DL, DL when the column j has been selected, in response to a signal CSL.sub.j supplied from column decoder 6 (FIG. 1) to the I/O gate transistors Q5 and Q6.
As the capacity of the semiconductor memory devices increases, the possibility that the devices will contain one or more defective memory cells also increases. This problem adversely affects the yield of the semiconductor memory device manufacturing process. One technique for dealing with this problem is to utilize redundancy memory cells which are provided in a semiconductor memory device to replace memory cells which have been determined to be defective during device testing. Accordingly, a word line or a bit line to which a defective memory cell is connected may be replaced by a redundant line attached to redundant memory cells. An address of a defective memory cell may be programmed by blowing appropriate ones of the fuses in a redundancy control circuit. A redundant memory cell is selected when an address corresponding to a defective memory cell is an input.
FIG. 3 illustrates a portion of a convention dynamic random access memory (DRAM) with row redundancy. Such a memory arrangement is described in U.S. Pat. No. 5,555,212 issued to Toshiaki Kirihata et al., of common assignees, which is herein incorporated by reference. The memory portion includes memory cells MC1, MC2 and a redundant memory cell RMC1. The memory cells MC1 and MC2 are formed by respective data storage capacitors Cs and transfer transistors Qs. The redundant memory cell RMC1 is formed by a data storage capacitor Cr and a transfer transistor Qr. The gates of the transfer transistors Qs of memory cells MC1, MC2 are respectively connected to word lines WL.sub.i and WL.sub.j. The gate of the transfer transistor Qr of redundant memory cell RMC1 is attached to a redundant word line RDWL.sub.i. External address signals are supplied via an address buffer (not shown) to a row decoder which generates word line selecting signals (RSLi, RSLj, . . . , etc.). The address buffer forwards address signals to redundancy control circuit RRDN. RRDN generates a word line drive signal WD and redundant word line drive signals RDWD.sub.1 , RDWD.sub.2 , . . . , and RDWD.sub.j . WD is activated when a memory cell on a normal word line is accessed, whereas one of the RDWDs becomes active when one of the redundant memory cells on a redundant word line is accessed. Signals WD and RDWD.sub.1 , RDWD.sub.2 , . . . , and RDWD.sub.j , are respectively forwarded to word line driver WDR and to the redundant word line driver RWDR. For each word line, the word line driver WDR is implemented as an AND gate. At each AND gate, WD is gated with the respective word line selecting signal RSL. When the word line WL.sub.i is driven by word line driver WDR, data may be read out or written in the data storage capacitor Cs of memory cell MC1 via bit line BL.sub.j. Similarly, when the word line WL.sub.j is driven by the word line driver WDR, data may be read out or written in the data storage capacitor Cs of the memory cell MC2 via bit line BL.sub.j . The redundant memory cell RMC1 may replace either memory cell MC1 or MC2 if it is determined that one of these cells is defective. However, it can be seen that if the redundant memory cell RMC1 replaces the memory cell MC2, the physical data stored in capacitor Cr of redundant memory cell RMC1, representing a given logical data bit, will be inverted with respect to the physical data stored in capacitor Cs of memory cell MC2, representing the same given logical data bit. In general, in semiconductor memory cell devices such as DRAMs, two logic states correspond to the arrangement and composition of the memory cell array. Half the memory cells equal the true state of data to be read or written, while the other half corresponds to the complementary state.
When a defective memory cell is detected and replaced by a redundant memory cell, the physical data state (i.e., bit pattern) in which a given bit is stored in a substituted redundant memory cell may differ (i.e., be inverted) from the physical data state in which the given bit is stored in the replaced memory cell.
Shown in FIG. 4 are word line drivers 20, a memory cell array including a word line WLi, a redundant memory cell array including a redundant word line RDWLJ, and sense amplifiers 30. According to this arrangement, a redundant word line, such as RDWL.sub.j, may be substituted for a defective word line WL.sub.i. When RDWL.sub.j replaces WL.sub.i, the bit information will be inverted because the physical data states of the memory cells respectively coupled to word lines WL.sub.i and RDWL.sub.j are complementary. As a result, this architecture fails to maintain the original physical bit information. Consequently, during testing of the semiconductor memory device, both the logical 1 and logical 0 data, must be supplied to the memory device in order, for example, to write physical 1 data to all the memory cells including the redundant memory cells. Likewise, both logical 1 and logical 0 data must be supplied to the memory device in order to write physical 0 data to all the memory cells including the redundant memory cells. The testing time for such a scheme is, therefore, long.
The conventional approach that has successfully been used to overcome this problem is further described in the aforementioned U.S. Pat. No. 5,555,212, wherein the data pattern on the DL pairs is manipulated when a bit map inconsistency occurs. By way of example, when WLj, which couples BL and DL to CSL, is replaced with RDWLj, which couples BL and DL to CSL, the data pattern on DL and DL ends up being swapped. The inverted data pattern to the corresponding BL is transferred, allowing consistency of the bit map to be maintained. It requires, however, that logic be incorporated on the data path, which results in a substantial penalty on the column access speed.